The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, device performance can be improved by using a high-k metal gate structure (HKMG) instead of a polysilicon gate. While existing methods have generally been adequate, challenges remain in implementing such method, especially with respect to forming multiple conductive layers in the HKMG when feature sizes (e.g., gate lengths) continue to decrease.